In semiconductor design, standard cell methodology typically involves designing integrated circuits having various functionality using standard components and interconnect structures. These activities are typically facilitated within a computer aided design environment. Standard cell methodology uses abstraction wherein low level integrated circuit synthesis is replaced by a more abstract, higher-level functional representation. Cell-based methodologies allow designers to focus on the high-level aspect of design. A standard cell can be made up of a group of transistor structures, passive structures, and interconnect structures that make up atomic functions such as logic functions, storage functions or the like. When the cell design is completed, fabrication may be performed to carry out the physical implementation.
Polylines are graphical objects offered as part of conventional computer aided design packages. Polylines may be used during the design stage to define features associated with devices that are patterned onto semiconductors. During fabrication, the polylines may be formed onto the semiconductor and subsequently altered in various stages in the process of realizing the devices.
The width of the polyline typically determines the channel length of devices within the cells, and thus influences their threshold voltage value VT. Due, in part, to the resolution issues associated with conventional photolithographic equipment, it is customary, when designing certain devices such as integrated transistor devices, to use uniform sized polylines having the same channel length for devices in a particular pattern. Since devices associated with the polyline are designed to operate from the same voltage VT, and since the resolution has been historically insufficient to allow deviations from the conventional approach, convention standard cell library design has seldom been questioned.
In some instances, it may be advantageous to fabricate devices having differing channel lengths (and thus differing threshold voltages) on a common semiconductor substrate. This effort entails patterning polylines having differing line widths over separate active regions. Existing patterning techniques may be used to realize such devices, however, they can result in polylines having tapering characteristics in the region where the channel length changes. Such tapering may lead to undesirable process variation, and can increase the spacing between the active regions to values over 170 nm, which can lead to inefficiencies in manufacturing and reduced process yields.